Cell based integrated circuit and unit cell architecture therefor

ABSTRACT

In a method for designing a unit cell, a first conductive type active region and a second conductive type active region are provided. Those two active regions extend in a first direction. Each of the active regions has first and second ends thereof. The first end of the second conductive type active regions is opposing to the second end of the first conductive type active region. In the method, a poly-silicon pattern is provided to extend in the first direction across the first conductive type active region and second conductive type active region. A first contact region is arranged adjacent the first end of the first conductive type active region in the first direction. A second contact region is arranged adjacent the second end of the second conductive type active region in the first direction.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates to cell based integrated circuitsand unit cell architecture for such circuits, which result insignificant improvement of the degree of integration.

BACKGROUND OF THE INVENTION

[0002] Cell based integrated circuit technology and cell architecturefor such circuits have been developed as quick-turns integrated circuit(IC) design methodologies in which pre-designed circuit units or cellsare wired together to rapidly implement a new IC functionality. Thepre-designed circuit elements are called macro cells which are made byinterconnecting unit cells.

[0003] A conventional unit cell includes a P-type active region (PMOStransistor) and an N-type active region (NMOS transistor), which arearranged in a first direction. A pair of poly-silicon regions is formedon each of the P-type and N-type active regions. Those poly-siliconregions are extending in parallel to each other in the first direction.The unit cell also includes first and second substrate contact regions,which are arranged in parallel to the P-type active region and N-typeactive region respectively.

[0004] When a circuit, such as a macrolibrary, is made, the poly-siliconregions on the P-type active region are connected to the poly-siliconregions on the N-type active region with conductive lines.

[0005] According to the conventional unit cell, power line (Vdd) andground line (Vss) across the P-type active region and N-type activeregion; therefore the arrangement of conductive lines becomescomplicated. To prevent intersection between signal lines and powerline/ground line, the signal lines should be formed on a different layerfrom the power line and ground line. As a result, it becomes difficultto increase the degree of integration of the IC.

[0006] Further, conductive lines connecting the poly-silicon lines onthe P-type active region and N-type active regions may across the signallines, therefore the arrangement of conductive lines becomescomplicated. To prevent intersection between such conductive lines andthe signal lines, the signal lines should be formed on a differentlayer. As a result, it becomes difficult to increase the degree ofIntegration of the IC.

OBJECTS OF THE INVENTION

[0007] Accordingly, an object of the present invention is to provide amethod for designing a unit cell that contributes for increasing thedegree of integration of the integrated circuit.

[0008] Another object of the present invention is to provide a unit cellthat contributes for increasing the degree of integration of theintegrated circuit.

[0009] Further object of the present invention is to provide anintegrated circuit of which the degree of integration can be increased.

[0010] Additional objects, advantages and novel features of the presentinvention will be set forth in part in the description that follows, andin part will become apparent to those skilled in the art uponexamination of the following or may be learned by practice of theinvention. The objects and advantages of the invention may be realizedand attained by means of the instrumentalities and combinationsparticularly pointed out in the appended claims.

SUMMARY OF THE INVENTION

[0011] According to a first aspect of the present invention, in a methodfor designing a unit cell, a first conductive type active region and asecond conductive type active region are provided. Those two activeregions are arranged to extend in a first direction. Each of the activeregions has first and second ends thereof. The first end of the secondconductive type active regions is opposing to the second end of thefirst conductive type active region. In the method, a poly-siliconpattern is provided to extend in the first direction across the firstconductive type active region and second conductive type active region.A first contact region is arranged adjacent the first end of the firstconductive type active region in the first direction. A second contactregion is arranged adjacent the second end of the second conductive typeactive region in the first direction.

[0012] Preferably, the first conductive type active region is formed tohave a projecting region at the first end, which extends in the firstdirection toward the first contact region; and the second conductivetype active region is formed to have a projecting region at the secondend, which extends in the first direction toward the second contactregion.

[0013] The poly-silicon pattern may extend in the first directioncontinuously without any break therein.

[0014] According to a second aspect of the present invention, a unitcell that is designed by a method according to the above described firstaspect of the present invention.

[0015] According to a third aspect of the present invention, anintegrated circuit that is made by a unit cell according to the abovedescribed second aspect of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a plan view showing a conventional unit cellarchitecture.

[0017]FIG. 2 is a plan view showing an inverter that is made with theconventional unit cell, shown in FIG. 1.

[0018]FIG. 3 is a plan view showing a unit cell architecture accordingto a first preferred embodiment of the present invention.

[0019]FIG. 4 is a plan view showing a unit cell architecture accordingto a second preferred embodiment of the present invention.

[0020]FIG. 5 is a plan view showing a unit cell architecture accordingto a third preferred embodiment of the present invention.

[0021]FIG. 6 is a plan view showing a unit cell architecture accordingto a fourth preferred embodiment of the present invention.

[0022]FIG. 7 is a plan view showing a two-input NAND gate that is madewith the unit cell, shown in FIG. 3.

[0023]FIG. 8 is a plan view showing a multiplexor that is made with theunit cell, shown in FIG. 3.

DETAILED DISCLOSURE OF THE INVENTION

[0024] In the following detailed description of the preferredembodiments, reference is made to the accompanying drawings which form apart hereof, and in which is shown by way of illustration specificpreferred embodiments in which the inventions may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be utilized and that logical, mechanical andelectrical changes may be made without departing from the spirit andscope of the present inventions. The following detailed description is,therefore, not to be taken in a limiting sense, and scope of the presentinventions is defined only by the appended claims.

[0025] For better understanding of the present invention, a conventionaltechnology is first described. FIG. 1 shows a conventional unit cellarchitecture. The unit cell includes an N-type well contact region 10(N+contact region) for Vdd (distributed power); a substrate contactregions 12 (P+contact region) for Vss (ground); a P+active region 18; anN+active region 20; and poly-silicon patterns 22 a, 22 b, 22 c and 22 d.The P+active region 18 is formed on an N-type well region 26.

[0026] The P+active region 18 and N+active region 20 are arranged toextend in a first direction, between the top and bottom in the drawing.The N-type well contact region 10 is arranged in parallel to theP+active region 18. The substrate contact region 12 is arranged inparallel to the N+active region 20. Each of the poly-silicon patterns 22a-22 d extends in the first direction, between the top and bottom of thearchitecture.

[0027] The N-type well contact region 10 is connected to a power supply(Vdd) line 14, which extends in a second direction orthogonal to thefirst direction. In the same manner, the substrate contact region 12 isconnected to a ground (Vcc) line 16, which extends in the seconddirection.

[0028]FIG. 2 shows an inverter that is made with the conventional unitcell, shown in FIG. 1. In the inverter, the P+active region 18 andN+active region 20 are connected to each other by a conductive line 32.The poly-silicon patterns 22 a and 22 c are connected to each other by aconductive line 30. One portion of the P+active region 18 is connectedto the substrate contact region 10 by the power supply line 14. Oneportion of the N-type active region 20 is connected to the substratecontact region 12 by the ground line 16.

[0029] According to the conventional unit cell, the power line 14 andground line 16 are arranged to across the P+active region 18 andN+active region 20 in the orthogonal direction; therefore thearrangement of conductive lines becomes complicated. To preventintersection between signal lines and power/ground lines, the signallines should be formed on a different layer from the power line andground line. As a result, it becomes difficult to increase the degree ofintegration of the IC.

[0030] Further, conductive lines connecting the poly-silicon patternsmay across the signal lines, therefore the arrangement of conductivelines becomes complicated. To prevent intersection between suchconductive lines and the signal lines, the signal lines should be formedon a different layer. As a result, it becomes difficult to increase thedegree of integration of the IC.

[0031]FIG. 3 shows a unit cell architecture 100 according to a firstpreferred embodiment of the present invention. The unit cell 100includes an N-type well contact region 110 (N+contact region) for Vdd(distributed power); a substrate contact regions 112 (P+contact region)for Vss (ground); a P+active region 118; an N+active region 120; andpoly-silicon patterns 122 a and 122 b, including gate electrode portionand terminal.

[0032] The P+active region 118 and N-type well contact region 110 areformed on an N-type well region 126.

[0033] Metal layers 111 and 113 are formed over the substrate contactregion (N+contact region) 110 and substrate contact region (P+contactregion) 112, respectively. The substrate contact region 110 is providedwith contacts 110 a, which make electrical contact to the metal layer111. In the same manner, the substrate contact region 112 is providedwith contacts 112 a, which make electrical contact to the metal layer113.

[0034] The P+active region 118 and N+active region 120 are arranged toextend in a first direction, between the top and bottom of thearchitecture. The poly-silicon patterns 122 a and 122 b are arranged toextend in the first direction as well to across the P+active region 118and N+active region 120. In other words, those two poly-silicon patterns122 a and 122 b extends continuously without any breaks between theP+active region 118 and N+active region 120.

[0035] The P+active region 118 is formed to have first and second endsthereof, in which the first end is opposing to the N-type well contactregion 110. The P+active region 118 is shaped to have a projectingregion 118 a at the first end thereof. In other words, the projectingregion 118 a extends toward the substrate contact region 110.

[0036] The N+active region 120 is formed to have first and second endsthereof, which respectively oppose to the second end of the P+activeregion 118 and the substrate contact region 112. The N+active region 120is shaped to have a projecting region 120 a at the second end thereof.The projecting region 120 a extends toward the substrate contact region112.

[0037] The N+contact region 110 is arranged adjacent to the first end ofthe P+active region 118 in the first direction. In the same manner, thesubstrate contact region 112 is arranged adjacent to the second end ofthe N+active region 118 in the first direction.

[0038] In fabrication, the N type well region 126 is first formed, andthen the P+ions are introduced into the substrate to form the P+activeregions 118 and the P+contact regions 112. Then, N+ions are introducedinto the substrate to form the N+active region 120 and the N+contactregion 110. The poly-silicon gate pattern including terminals 122 a and122 b are formed, and then the metal layers 111 and 113 are formed overthe N+contact region 110 and P+contact region 112, respectively. Themetal layers 110 and 118 are electrically connected to the N+contactregion 110 and P+contact region 112 via the contacts (or using throughholes) 110 a and 112 a, respectively. The metal layers 111 and 113 areto be connected to another metal layer (second metal layer) usingthrough holes.

[0039] According to the unit cell 100, the contact regions 110 and 112are arranged at the top and bottom ends of the architecture 100, so thatpower line and ground line are arranged to extend in the seconddirection without crossing the active regions 118 and 120. Therefore, itis not always required to form signal lines on a different layer toprevent intersection between those signal lines and the power/groundlines. Further, the poly-silicon patterns 122 a and 122 b extend throughthe P+active region 118 and N+active region 120, so that no conductiveline is necessary to connect the poly-silicon terminals to each other.Such architecture allows the integrated circuit to increase the degreeof integration.

[0040]FIG. 4 shows a unit cell architecture according to a secondpreferred embodiment of the present invention. The unit cell 200includes an N-type well contact region 210 (N+contact region) for Vdd(distributed power); a substrate contact regions 212 (P+contact region)for Vss (ground); a P+active region 218; an N+active region 220; andpoly-silicon patterns 222 a and 222 b.

[0041] The P+active region 218 and N+contact region 210 are formed on anN-type well region 226.

[0042] Metal layers 211 and 213 are formed over the contact regions 210and 212, respectively. The N+contact region 210 is provided withcontacts 210 a for making electrical contact to the metal layer 211. Inthe same manner, the P+contact region 212 is provided with contacts 212a for making electrical contact to the metal layer 213.

[0043] The P+active region 218 and N+active region 220 are arranged toextend in a first direction, between the top and bottom of thearchitecture. The poly-silicon patterns 222 a and 222 b are arranged toextend in the first direction as well to across the P+active region 218and N+active region 220. In other words, those two poly-silicon patterns222 a and 222 b extends continuously without any breaks between theP+active region 218 and N+active region 220. The poly-silicon layer(pattern) 222 a is connected at the top and bottom ends to the contactregions 210 and 212, respectively. In the same manner, the poly-siliconlayer (pattern) 222 b is connected at the top and bottom ends to thesubstrate contact regions 210 and 212, respectively.

[0044] The P+active region 218 is formed to have first and second endsthereof, in which the first end is opposing to the N+contact region 210.The N+active region 220 is formed to have first and second ends thereof,which respectively oppose to the second end of the P+active region 218and the P+contact region 212.

[0045] The N+contact region 210 is arranged adjacent to the first end ofthe P+active region 218 in the first direction. In the same manner, theP+contact region 212 is arranged adjacent to the second end of theN+active region 218 in the first direction.

[0046] In fabrication, the N type well region 226 is first formed, andthen the P+ions are introduced into the substrate to form the P+activeregions 218 and the P+contact regions 212. Then, N+ions are introducedinto the substrate to form the N+active region 220 and the N+contactregion 210. The poly-silicon gate pattern including terminals 222 a and222 b are formed, and then the metal layers 211 and 213 are formed overthe N+contact region 210 and P+contact region 212, respectively. Themetal layers 210 and 218 are electrically connected to the N+contactregion 210 and P+contact region 212 via the contacts (or using throughholes) 210 a and 212 a, respectively. The metal layers 211 and 213 areto be connected to another metal layer (second metal layer) usingthrough holes.

[0047] According to the unit cell 200, the contact regions 210 and 212are arranged at the top and bottom ends of the architecture 200, so thatpower line and ground line are arranged to extend in the seconddirection without crossing the active regions 218 and 220. Therefore, itis not always required to form signal lines on a different layer toprevent intersection between those signal lines and the power/groundlines. Further, the poly-silicon patterns 222 a and 222 b extend throughthe P+active region 218 and N+active region 220, so that no conductiveline is necessary to connect the poly-silicon patterns to each other.Such architecture allows the integrated circuit to increase the degreeof integration.

[0048]FIG. 5 shows a unit cell architecture according to a thirdpreferred embodiment of the present invention. The unit cell 300includes a N-type well contact region 310 (N+contact region) for Vdd(distributed power); a substrate contact regions 312 (P+contact region)for Vss (ground); a P+active region 318; an N+active region 320; andpoly-silicon patterns 322 a and 322 b.The P+active region 318 is onegrid longer than the P+active region 218 of the second preferredembodiment, shown in FIG. 4.

[0049] The P+active region 318 and N+contact region 310 are formed on anN-type well region 326.

[0050] The P+active region 318 and N+active region 320 are arranged toextend in a first direction, top and bottom in the drawing of FIG. 5.The poly-silicon patterns 322 a and 322 b are arranged to extend in thefirst direction as well to across the P+active region 318 and N+activeregion 320. In other words, those two poly-silicon patterns 322 a and322 b extends continuously without any breaks between the P+activeregion 318 and N+active region 320. The poly-silicon layer (pattern) 322a is connected at the top and bottom ends to the substrate contactregions 310 and 312, respectively. In the same manner, the poly-siliconlayer (pattern) 322 b is connected at the top and bottom ends to thecontact regions 310 and 312, respectively.

[0051] A The P+active region 318 is formed to have first and second endsthereof, in which the first end is opposing to the N+contact region 310.The N+active region 320 is formed to have first and second ends thereof,which respectively oppose to the second end of the P+active region 318and the P+contact region 312.

[0052] Metal layers 311 and 313 are formed over the contact regions 310and 312, respectively. The N+contact region 310 is provided withcontacts 310 a for making electrical contact to the metal layer 311. Inthe same manner, the P+contact region 312 is provided with contacts 312a for making electrical contact to the metal layer 313.

[0053] The N+contact region 310 is arranged adjacent to the first end ofthe P+active region 318 in the first direction. In the same manner, theP+contact region 312 is arranged adjacent to the second end of theN+active region 318 in the first direction.

[0054] In fabrication, the N type well region 326 is first formed, andthen the P+ions are introduced into the substrate to form the P+activeregions 318 and the P+contact regions 312. Then, N+ions are introducedinto the substrate to form the N+active region 320 and the N+contactregion 310. The poly-silicon gate pattern including terminals 322 a and322 b are formed, and then the metal layers 311 and 313 are formed overthe N+contact region 310 and P+contact region 312, respectively. Themetal layers 310 and 318 are electrically connected to the N+contactregion 310 and P+contact region 312 via the contacts (or using throughholes) 310 a and 312 a, respectively. The metal layers 311 and 313 areto be connected to another metal layer (second metal layer) usingthrough holes.

[0055] According to the unit cell 300, the contact regions 310 and 312are arranged at the top and bottom ends of the architecture 300, so thatpower line and ground line are arranged to extend in the seconddirection without crossing the active regions 318 and 320. Therefore, itis not always required to form signal lines on a different layer toprevent intersection between those signal lines and the power/groundlines. Further, the poly-silicon patterns 322 a and 322 b extend throughthe P+active region 318 and N+active region 320, so that no conductiveline is necessary to connect the poly-silicon patterns to each other.Such architecture allows the integrated circuit to increase the degreeof integration. Finally, since the P+active regions 318 has longdimension, PMOS transistors formed in P+active region 318 have improvedconductance.

[0056]FIG. 6 shows a unit cell architecture 400 according to a fourthpreferred embodiment of the present invention. The unit cell 400includes an N-type well contact region 410 (N+contact region) for Vdd(distributed power); a substrate contact regions 412 (P+contact region)for Vss (ground); a P+active region 418; an N+active region 420; andpoly-silicon patterns 422 a, 422 b and 422 c.

[0057] The P+active region 418 and N+contact region 410 are formed on anN-type well region 426.

[0058] The P+active region 418 and N+active region 420 are arranged toextend in a first direction, top and bottom in the drawing of FIG. 6.The poly-silicon patterns 422 a, 422 b and 422 c are arranged to extendin the first direction. The poly-silicon pattern 422 a is extendingacross both the P+active region 418 and N+active region 420. Thepoly-silicon pattern 422 b is extending across only the P+active region418, while the poly-silicon pattern 422 c is extending across only theN+active region 420.

[0059] The P+active region 418 is formed to have first and second endsthereof, in which the first end is opposing to the N+contact region 410.The P+active region 418 is shaped to have a projecting region 418 a atthe first end thereof. In other words, the projecting region 418 aextends toward the N+contact region 410.

[0060] The N+active region 420 is formed to have first and second endsthereof, which respectively oppose to the second end of the P+activeregion 418 and the P+contact region 412. The N+active region 420 isshaped to have a projecting region 420 a at the second end thereof. Theprojecting region 420 a extends toward the P+contact region 412.

[0061] Metal layers 411 and 413 are formed over the N+contact region 410and P+contact region 412, respectively. The N+contact region 410 isprovided with contacts 410a, which make electrical contact to the metallayer 411. In the same manner, the P+contact region 412 is provided withcontacts 412 a, which make electrical contact to the metal layer 413.

[0062] The N+contact region 410 is arranged adjacent to the first end ofthe P+active region 418 in the first direction. In the same manner, theP+contact region 412 is arranged adjacent to the second end of theN+active region 418 in the first direction.

[0063] In fabrication, the N type well region 426 is first formed, andthen the P+ions are introduced into the substrate to form the P+activeregions 418 and the P+contact regions 412. Then, N+ions are introducedinto the substrate to form the N+active region 420 and the N+contactregion 410. The poly-silicon gate pattern including terminals 422 a, 422b and 422 c are formed, and then the metal layers 411 and 413 are formedover the N+contact region 410 and P+contact region 412, respectively.The metal layers 410 and 418 are electrically connected to the N+contactregion 410 and P+contact region 412 via the contacts (or using throughholes) 410 a and 412 a, respectively. The metal layers 411 and 413 areto be connected to another metal layer (second metal layer) usingthrough holes.

[0064] According to the unit cell 400, the substrate contact regions 410and 412 are arranged at the top and bottom ends of the architecture 400,so that power line and ground line are arranged to extend in the seconddirection without crossing the active regions 418 and 420. Therefore, itis not always required to form signal lines on a different layer toprevent intersection between those signal lines and the power/groundlines. Further, the poly-silicon patterns 422 b and 422 c are formed tobe separated from each other, so that an integrated circuit can bedesigned flexibly as compared to the first preferred embodiment, shownin FIG. 3.

[0065]FIG. 7 shows a two-input NAND gate 500 that is made with the unitcell 100, shown in FIG. 3. In the circuit 500, the N+contact region 110is connected to outer portions of the P+active region 118 by conductivelines 502 and 504. One of the outer portions of the P+active region 118is connected to the poly-silicon pattern 122 a by a conductive line 506.An inner portion of the P+active region 118 is also connected to one ofthe outer portions of the N+active region 120 by a conductive line 510.The poly-silicon pattern 122 b is connected to the other outer portionof the N+active region 120 by a conductive line 508. The other outerportion of the N+active region 120 is also connected to the P+contactregion 112 by a conductive line 512.

[0066]FIG. 8 shows a multiplexer that is made with the unit cells 100,shown in FIG. 3. In FIG. 8, a reference numeral 602 indicates a N typewell region.

[0067] According to the present invention, substrate contact regions arearranged at the top and bottom ends of unit cell architecture, theintegrated circuit is improved in degree of integration. Further, whenpoly-silicon patterns are arranged to extend through P+active region andN+active region, no conductive line is necessary to connect thepoly-silicon patterns to each other. That also allows the integratedcircuit to increase the degree of integration.

What is claimed is:
 1. A method of designing a unit cell, which is usedfor making an integrated circuit, comprising the steps of: providing afirst conductive type active region, which extends in a first directionto have first and second ends thereof; providing a second conductivetype active region, which extends in the first direction to have firstand second ends thereof, the first end opposing to the second end of thefirst conductive type active region; providing a poly-silicon patternextending in the first direction across the first and second conductivetype active regions; providing a first contact region adjacent to thefirst end of the first conductive type active region in the firstdirection; and providing a second contact region adjacent to the secondend of the second conductive type active region in the first direction.2. A method according to claim 1, wherein the first conductive typeactive region is formed to have a projecting region at the first end,which extends in the first direction toward the first substrate contactregion; and the second conductive type active region is formed to have aprojecting region at the second end, which extends in the firstdirection toward the second substrate contact region.
 3. A methodaccording to claim 1, wherein the poly-silicon pattern extends in thefirst direction continuously without no break therein.
 4. A methodaccording to claim 1, wherein the poly-silicon pattern is formed to bein contact with the first and second contact regions.
 5. A method ofdesigning a unit cell, which is used for making an integrated circuit,comprising the steps of: providing a first conductive type activeregion, which extends in a first direction to have first and second endsthereof; providing a second conductive type active region, which extendsin the first direction to have first and second ends thereof, the firstend opposing to the second end of the first conductive type activeregion; providing a pair of poly-silicon patterns each extendingcontinuously in parallel to each other in the first direction across thefirst conductive type active region and second conductive type activeregion; providing a first contact region adjacent to the first end ofthe first conductive type active region in the first direction; andproviding a second contact region adjacent to the second end of thesecond conductive type active region in the first direction, wherein thefirst conductive type active region is formed to have a projectingregion at the first end, which extends in the first direction toward thefirst substrate contact region; the second conductive type active regionis formed to have a projecting region at the second end, which extendsin the first direction toward the second substrate contact region; andthe poly-silicon patterns are formed to be in contact with none of thefirst and second substrate contact regions.
 6. A method according toclaim 1, wherein each of the poly-silicon patterns is formed to be incontact with the first and second substrate contact regions.
 7. A methodaccording to claim 1, wherein each of the poly-silicon patternscomprises two line regions in which one of them is divided between thefirst conductive type active region and second conductive type activeregion.
 8. A unit cell for an integrated circuit, comprising: a firstconductive type active region, which extends in a first direction tohave first and second ends thereof; a second conductive type activeregion, which extends in the first direction to have first and secondends thereof, the first end opposing to the second end of the firstconductive type active region; a poly-silicon pattern extending in thefirst direction across the first conductive type active region andsecond conductive type active region; a first contact region that isarranged adjacent to the first end of the first conductive type activeregion in the first direction; and a second contact region that isarranged adjacent to the second end of the second conductive type activeregion in the first direction.
 9. A unit cell according to claim 8,wherein the first conductive type active region is formed to have aprojecting region at the first end, which extends in the first directiontoward the first substrate contact region; and the second conductivetype active region is formed to have a projecting region at the secondend, which extends in the first direction toward the second substratecontact region.
 10. A unit cell according to claim 8, wherein thepoly-silicon pattern extends in the first direction continuously withoutno break therein.
 11. A unit cell according to claim 8, wherein thepoly-silicon pattern is formed to be in contact with the first andsecond contact regions.
 12. A unit cell for an integrated circuit,comprising: a first conductive type active region, which extends in afirst direction to have first and second ends thereof; a secondconductive type active region, which extends in the first direction tohave first and second ends thereof, the first end opposing to the secondend of the first conductive type active region; a pair of poly-siliconpatterns each extending continuously in parallel to each other in thefirst direction across the first conductive type active region andsecond conductive type active region; a first contact region that isarranged adjacent to the first end of the first conductive type activeregion in the first direction; and a second contact region that isarranged adjacent to the second end of the second conductive type activeregion in the first direction, wherein the first conductive type activeregion is formed to have a projecting region at the first end, whichextends in the first direction toward the first contact region; thesecond conductive type active region is formed to have a projectingregion at the second end, which extends in the first direction towardthe second contact region; and each of the poly-silicon patterns isformed to be in contact with none of the first and second substratecontact regions.
 13. A unit cell according to claim 8, wherein each ofthe poly-silicon patterns is formed to be in contact with the first andsecond substrate contact regions.
 14. A unit cell according to claim 8,wherein each of the poly-silicon patterns comprises two line regions inwhich one of them is divided between the first conductive type activeregion and second conductive type active region.
 15. An integratedcircuit that is made by a unit cell, which comprises: a first conductivetype active region, which extends in a first direction to have first andsecond ends thereof; a second conductive type active region, whichextends in the first direction to have first and second ends thereof,the first end opposing to the second end of the first conductive typeactive region; a poly-silicon pattern extending in the first directionacross the first conductive type active region and second conductivetype active region; a first contact region that is arranged adjacent tothe first end of the first conductive type active region in the firstdirection; and a second contact region that is arranged adjacent to thesecond end of the second conductive type active region in the firstdirection.
 16. An integrated circuit according to claim 15, wherein thefirst conductive type active region is formed to have a projectingregion at the first end, which extends in the first direction toward thefirst substrate contact region; and the second conductive type activeregion is formed to have a projecting region at the second end, whichextends in the first direction toward the second substrate contactregion.
 17. An integrated circuit according to claim 15, wherein thepoly-silicon pattern extends in the first direction continuously withoutno break therein.
 18. An integrated circuit according to claim 15,wherein the poly-silicon pattern is formed to be in contact with thefirst and second substrate contact regions.
 19. An integrated circuitthat is made by a unit cell, which comprises: a first conductive typeactive region, which extends in a first direction to have first andsecond ends thereof; a second conductive type active region, whichextends in the first direction to have first and second ends thereof,the first end opposing to the second end of the first conductive typeactive region; a pair of poly-silicon patterns each extendingcontinuously in parallel to each other in the first direction across thefirst conductive type active region and second conductive type activeregion; a first contact region that is arranged adjacent to the firstend of the first conductive type active region in the first direction;and a second contact region that is arranged adjacent to the second endof the second conductive type active region in the first direction,wherein the first conductive type active region is formed to have aprojecting region at the first end, which extends in the first directiontoward the first substrate contact region; the second conductive typeactive region is formed to have a projecting region at the second end,which extends in the first direction toward the second substrate contactregion; and each of the poly-silicon patterns is formed to be in contactwith none of the first and second substrate contact regions.
 20. Anintegrated circuit according to claim 15, wherein each of thepoly-silicon patterns is formed to be in contact with the first andsecond substrate contact regions.
 22. An integrated circuit according toclaim, wherein each of the poly-silicon patterns comprises two lineregions in which one of them is divided between the first conductivetype active region and second conductive type active region.